Ramachandran Varatharajan. Design and Analysis of Low Power High-Speed Full Adder Based Detection Combination Algorithm Using Finfet Technology. Neural, Parallel, and Scientific Computations 28 (2020) No.4, 261-272

https://doi.org/10.46719/npsc20202843

ABSTRACT:
It is an efficient implementation of the Fin-Fet arithmetic circuit used in providing processor making analytical tasks. The complementary metal-oxide-semiconductor leakage current depends on the driving capacity, which is delayed from the compression circuit. This method is based on any real-time digital signal processing application, where the drive current must be high. The conventional design will have a low-efficiency supply voltage with low capacitance; even when operating, the circuit speed will be faster, and the delay will be less. The method add-on structure is designed to select or transfer gates from input data to output. The proposed 10T full adder and adder is given in and respectively. Low operation Very low-level integrated circuit, capable of low power consumption, which has become an essential standard operation for the design of energy-efficient electronic products, has become the primary function and compact device design, once again possible. The coefficient plays a significant role in planning energy-saving processors and determining processor performance. The multiplier coding booth method is used to rearrange the input bits to reduce device usage. Changing the equal position of a given booth is the behavior of the booth decoder. Booth decoder increases the range of different zero’s. Therefore, the switching behavior is reduced to reduce the power consumption of the design further.

Keyword: Fin Field-effect transistor (Fin FET), CMOS (complementary Metal-oxide-semiconductor), Full adder